The present invention relates to a memory cell, a memory cell array and a method for producing the memory cell.
Electrical devices, for example, security controllers, micro controllers or chip cards, are implemented on a semiconductor device and comprise a storage element. Conventional storage elements e.g. are non-volatile mass storage elements like Flash elements. As semiconductor devices often comprise a huge number of storage elements or memory cells, the area of a memory cell needs to be reduced in order to enable an economic production of the semiconductor device by reducing the manufacturing costs due to the reduced chip area. Due to the fact that the NVM (NVM=Non Volatile Memory) is a significant compound of the chip card or the micro controller, the reduction of the area of the memory cell is of major importance for reducing the chip area of the semiconductor device. Because the number of memory cells on a semiconductor device also amounts to 36 k bytes, 260 k bytes or 1M bytes the memory of a semiconductor device is not only an item to be evaluated during the production definition of the semiconductor device, but also a major factor of the manufacturing costs of the semiconductor device. The required silicon area or chip area of the memory usually represents the lion's share of the total chip area of the semiconductor device.
Thus, a reduction or a decrease of the required area or chip area of the memory cell of the NVM affects the area of the chip by a multiple depending on the size of the memory, e.g. by a factor of 8000000 in the case of a memory with a size of 1M bytes. In case the NVM-related segment comprises 50% of the total chip area, a reduction of the area of the memory cell by 10% results in a reduction of the total chip area by 5%. This leads to a reduction of the manufacturing costs or the costs of production by 5%. Hence, a new concept for the structure of a memory cell is a key element for reducing the chip area and for decreasing the cost of manufacturing and thus creating an economically successful product.
A conventional memory cell comprises one or two transistors. Depending on the programming of a transistor, a threshold voltage is shifted upwards or downwards. Due to the value of the threshold voltage, a current through a cell comprising one or two transistors changes its value. The thus resulting difference in the current flow is detected by a sense amplifier and converted in a voltage, wherein this voltage has two logic values, 0 or 1. In a NOR-architecture of a memory array, each source region and each drain region needs to be contacted by a dedicated contact. These contacts require lavish silicon areas leading to an increase in the manufacturing costs. Therefore a modification of the structure of a memory cell can be a decisive step for reducing the required chip area.